Our services

---

Before going deeper we carry out a comprehensive feasibility study aiming to answer critical questions: What implementation IC architecture and circuits can achieve the performance requirements? What are the R&D costs, material costs, CMOS process technology node, production costs (chip size estimations, test time estimations and test solution investigations) behind your ASIC project? How do R&D cost compare with production costs? What is the share of test time versus die cost? Single- or Multi-site test?  What DfT concept?

As a risk-aware and cost-conscious service supplier, we run comprehensive Risk Assessments and integrate the Mitigation Plan in the project planning. 

ASIC architectures

• MEMS, Capacitive, Inductive, Resistive, Optical sensor interfaces
• MEMS capacitive sensing of proof mass position and acceleration
• Embedded MEMS functional fault detection in the signal chain of a sensing frontend for high fault detection coverage and uninterrupted measurement and diagnostic 
• Capacitance sensing with switched capacitor circuits, impedance IQ measurements, frequency change detection, Time-to-Digital methods
• LIDAR and direct ToF transceivers
• PPG optical sensing
• EMI-immune sensor frontends for Automotive sensors
• Inductive and Capacitive sensor interfaces based on synchronous demodulation 
• Sense-drive transceivers e.g. synchronous waveform generation, sensor driver, IQ demodulation, baseband chain (amplifier, filter, ADC, DSP...) 
• RF transceivers
• Feedback channels of control loops, such as PWM based controllers, class D amplifiers and DC-DC converters
• High-performance audio amplifiers with state of the art THD, SNR and power efficiency - class A, AB, H, D, low-level audio signal chain processing blocks

Process nodes

TSMC, SMIC, etc. wafer fabs
65nm, 90nm, 130nm (incl. SiGe RF), 180nm (incl. HV BCD), 350nm and legacy 

ASIC Device Specification describing the architecture, functions, pinout, package, block diagrams, and the implementation concept of blocks with min-max parameter limits.  We cooperate actively with you on the application related topics and assist you in topics related to industrialization, such as reliability and test.

Our system and feasibility study and detailed numerical models are the base for robust 3-sigma or 6-sigma min-max specifications of parameters and blocks.

The consistent data management between specification parameter limits and the performance verification limits is essential for achieving first-time performing silicon. 

Design for Test specifications define the test modes and access to internal signals and required digital commands of the control interface (I2C, SPI...) for debug and production test with ATE. The test modes are analog and digital e.g. Scan.

Lab Evaluation specifications describing the parametric tests and conditions, test HW concept and schematic, test instruments requirements and automation e.g. based on a PXI system.

Test Specifications describing the ATE based list of tests, parameter limits and methods for defect-screening test in production with low test time. We cooperate with experienced test engineers with a broad overview of test platforms and their performance. We can assist you with the drafting of specifications that would be executed by an ATE test development service partner.

Qualification Specifications and Plan define the qualification stress driven tests and conditions such as HTOL, HAST, ESD, etc. according to JEDEC or AEC-Q100. We can assist you with the drafting of specifications that would be executed by a reliability service partner.

Full-custom Analog/Mixed-Signal/Layout design of high-performance signal processing circuits:

• Continuous and discrete time analog circuits 
• Switched capacitor amplifiers, integrators, S/H, filters, correlated double sampling, offset canceling
• Synchronous demodulation, Chopper offset canceling
• High-performance amplifiers - solutions addressing a particular  tradeoff between bandwidth, gain, noise, power, etc.
• Offset compensation continuous loops, loop amplifiers and integrators
• Optical frontends based on linear photocurrent amplification (TIA based) with ambient-DC integrating feedback loops, high dynamic range
• Precise timing circuits (TDC), multi-phase VCO and delay lines
• PLL for clock frequency multipliers, radio synthesizers, demodulation, synchronization and tracking
• Oscillators - ring, current-capacitor, LC, quartz
• Active and passive filters, system design and implementation
• ADC: SAR, Flash, Pipelined, Sigma-Delta (continuous and discrete time) and hybrids
• DAC - capacitive binary array, resistive, current binary array...
• Voltage and current references, bandgaps, PTAT, temperature sensors
• Analog waveform generation based on numerical synthesis, counter and DAC, linear ramps, etc.
• HV circuits and protections
• Digital synchronous circuits part of analog blocks

Digital design

Our partner digital design team would specify and design a digital core for any required function related to register and memory management, signal processing and communication interfaces such as I2C and SPI, and a lot more.

Lab characterization with focus on generating statistically valid data and full parametric coverage are essential for enabling defect-oriented production test.  

We develop the HW and SW required for IC sample bring-up, validation, and upon request we perform the automated validation in our lab using proprietary characterization benches. 

We support the generation of characterization data necessary to enable a defect-oriented production test and golden samples correlation

Our application team develops state-of-the-art HW/SW demos, providing turn-key development from application requirements all the way through definition and BOM selection, PCB schematic and layout design, SW/FW design, towards  verified and debugged demo HW modules that you can control from our App.  

• Embedded firmware development for the major microcontroller and SoC platforms on the market
• Application SW (Apps) for most operating systems on the market
• Significant experience in bring-up of simultaneously new ASIC, new HW and new SW